Details: Sessions, Reception and Social Events


PDF version of the program and session details can also be downloaded HERE.

The venue of the conference is the Northwestern Pritzker School of Law (Rubloff Aspen Hall – RB150), in Chicago Downtown. Here is a detailed map.


Session 1: Automata and Tree Mining Optimization

Time: June 14 (Wednesday), 10:00 am -12:00 noon ; Chair: V Krishna Nandivada (IIT, Madras)

  1. 10:00-10:30 am: “Demystifying Automata Processing: GPUs, FPGAs or Micron’s AP?”, Marziyeh Nourian, Xiang Wang, Xiaodong Yu, Wu-Chun Feng and Michela Becchi
  2. 10:30-11:00 am: “Enabling Scalability-Sensitive Speculative Parallelization for FSM Computations”, Junqiao Qiu, Zhijia Zhao, Bo Wu, Abhinav Vishnu and Shuaiwen Leon Song
  3. 11:00-11:30 am: “SPIRIT: A Framework for Creating Distributed Recursive Tree Applications”, Nikhil Hegde, Jianqiao Liu and Milind Kulkarni
  4. 11:30-12:00 noon: “Frequent Subtree Mining on the Automata Processor: Challenges and Opportunities”, Elaheh Sadredini, Reza Rahimi, Ke Wang and Kevin Skadron

Session 2: GPUs – Part 1

Time: June 14 (Wednesday), 13:30 pm -15:00 pm; Chair: Gagan Agrawal (Ohio State University)

  1. 13:30-14:00 pm: “Novel HPC Techniques to Batch Execution of Many Variable Size BLAS Computations on GPUs”, Ahmad Abdelfattah, Azzam Haidar, Stanimire Tomov and Jack Dongarra
  2. 14:00-14:30 pm: “Packet Coalescing Exploiting Data Redundancy in GPGPU Architectures”, Kyung Hoon Kim, Rahul Boyapati, Jiayi Huang, Yuho Jin, Ki Hwan Yum and Eun Jung Kim
  3. 14:30-15:00 pm: “Dynamic Scheduling for Efficient Hierarchical Sparse Matrix Operations on the GPU”, Andreas Derler, Rhaleb Zayer, Hans-Peter Seidel and Markus Steinberger

Session 3: Compilation Techniques

Time: June 14 (Wednesday), 15:30 pm -17:30 pm; Chair: Kyle Hale (Illinois Institute of Technology)

  1. 15:30-16:00 pm: “Compile-Time Optimized and Statically Scheduled N-D ConvNet Primitives for Multi-Core and Many-Core (Xeon Phi) CPUs”, Aleksandar Zlateski and H Sebastian Seung
  2. 16:00-16:30 pm: “HPAT: High Performance Analytics with Scripting Ease-of-Use”, Ehsan Totoni, Todd A. Anderson and Tatiana Shpeisman
  3. 16:30-17:00 pm: “On Improving Performance of General Sparse Matrix-Matrix Multiplication on GPUs”, Rakshith Kunchum, Ankur Chaudhry, Aravind Sukumaran-Rajam, Qingpeng Niu, Israt Nisa and P Sadayappan
  4. 17:00-17:30 pm: “Optimizing Recursive Task Parallel Programs”, Suyash Gupta, Rahul Shrivastava and V. Krishna Nandivada

 Session 4: GPUs – Part 2

Time: June 15 (Thursday), 10:00 am -12:00 pm; Chair: Woongki Baek (UNIST)

  1. 10:00-10:30 am: “Fast Segmented Sort on GPUs”, Kaixi Hou, Weifeng Liu, Hao Wang and Wu-Chun Feng
  2. 10:30-11:00 am: “Globally Homogeneous, Locally Adaptive Sparse Matrix-Vector Multiplication on the GPU”, Markus Steinberger, Rhaleb Zayer and Hans-Peter Seidel
  3. 11:00-11:30 am: “Simplification and Run-time Resolution of Data Dependence Constraints for Loop Transformations”, Diogo Sampaio, Louis-Noël Pouchet and Fabrice Rastello
  4. 11:30-12:00 noon: “A Performance Analysis Framework for Exploiting GPU Microarchitectural Capability”, Keren Zhou, Guangming Tan, Xiuxia Zhang, Chaowei Wang and Ninghui Sun

Session 5: Application Load Imbalance, Task and Data Mapping

Time: June 15 (Thursday), 13:30 pm -15:00 pm; Chair: Lei Liu (ICT, Chinese Academy of Sciences)

  1. 13:30-14:00 pm: “GraphGrind: Addressing Load Imbalance of Graph Partitioning”, Jiawen Sun, Hans Vandierendonck and Dimitrios Nikolopoulos
  2. 14:00-14:30 pm: “Automatic Topology Mapping of Diverse Large-scale Parallel Applications”, Juan J Galvez, Nikhil Jain and Laxmikant V. Kale
  3. 14:30-15:00 pm: “Design and Implementation of Bandwidth-Aware Memory Placement and Migration Policies for Heterogeneous Memory Systems”, Seongdae Yu, Seongbeom Park and Woongki Baek

 Session 6: Hardware Design

Time: June 15 (Thursday), 15:30 pm -16:30 pm; Chair: Michela Becchi (North Carolina State University)

  1. 15:30-16:00 pm: “Carpool: A Bufferless On-Chip Network Supporting Adaptive Multicast and Hotspot Alleviation”, Xiyue Xiang, Wentao Shi, Saugata Ghose, Lu Peng, Onur Mutlu and Nian-Feng Tzeng
  2. 16:00-16:30 pm: “Way-Combining Directory: An Adaptive and Scalable Low-Cost Coherence Directory”, Rubén Titos-Gil, Antonio Flores, Ricardo Fernández-Pascual, Alberto Ros and Manuel E. Acacio

Session 7 : Runtimes and  algorithms for parallel-application performance and reliability support

Time: June 16 (Friday), 08:30 am -10:00 am; Chair: Markus Steinberger (Max Planck Institute for Informatics)

  1. 08:30-09:00 am: “Iteration-Fusing Conjugate Gradient”, Sicong Zhuang and Marc Casas
  2. 09:00 – 09:30 am: “Supporting Automatic Recovery in Offloaded Distributed Programming Models Through MPI-3 Techniques”, Antonio J. Peña, Vicenç Beltran, Carsten Clauss and Thomas Moschn
  3. 09:30-10:00 am: “HiPA: History-based Piecewise Approximation for Functions”, Aurangzeb and Rudolf Eigenmann

Session 8: Data Aggregation and Hardware/Software Co-design Approaches

Time: June 16 (Friday), 10:30 am -13:00 pm; Chair: Manuel Acacio (Universidad de Murcia)

  1. 10:30-11:00 am: “Efficient SIMD and MIMD Parallelization of Hash-based Aggregation by Conflict Mitigation”, Peng Jiang and Gagan Agrawal
  2. 11:00-11:30 am: “Revisiting Phased Transactional Memory”, João P. L. de Carvalho, Alexandro Baldassin and Guido Araujo
  3. 11:30-12:00 noon: “Hardware/Software Cooperative Caching for Hybrid DRAM/NVM Memory Architectures”, Haikun Liu, Yujie Chen, Xiaofei Liao, Hai Jin, Bingsheng He, Long Zheng and Rentong Guo
  4. 12:00-12:30 pm: “SSDUP: A Traffic-Aware SSD Burst Buffer for HPC Systems”, Xuanhua Shi, Ming Li, Wei Liu, Hai Jin, Chen Yu and Yong Chen
  5. 12:30-13:00 pm: “libPRISM: An Intelligent Adaption of Prefetch and SMT Levels”, Cristobal Ortega, Miquel Moretó, Marc Casas, Ramon Bertran, Alper Buyuktosunoglu, Alexandre Eichenberger and Pradip Bose


Time : June 14th (Wednesday), 18:00-20:00pm

Location : Thorne Auditorium Lobby (Behind Rubloff Hall)

The ICS’17 reception will be held on June 14th, from 6pm onwards.


Time : June 15th (Thursday), 17:30-20:00pm

The ICS’17 conference has organized a boat cruise on the waters of Lake Michigan. A ticket for the cruise will be provided to you at the registration counter when you pick up your badge. Please ensure that you have the ticket with you when you arrive for the cruise. There will be no admittance without a ticket. Dinner will be served on the cruise.

The cruise boarding is to begin at 5:30pm (17:30). The cruise will depart from Navy Pier at 6:00 pm (18:00) sharp and we are expected to return by 8:00 pm (20:00).

All attendees are to arrive at Navy Pier for the boarding. The address is: 600 E Grand Avenue • Chicago, IL 60611 . Parking information can be found at the Spirit Cruises page. A map of Navy Pier showing where the Spirit docks can be found HERE.

Directions from the conference center are available here. Please do NOT cross Lake Shore Drive (it is under construction and is unsafe), just walk south to the underpass and cross under Lake Shore Drive.